The quantum wire.

A Jülich preprint compares error-correction-related circuit primitives across IBM, IQM and Quantinuum processors. Helios shows lower effective hardware error in selected comparisons; the benchmark tests building blocks rather than complete fault-tolerant applications.

Error-correction tools, Nighthawk r2 access and the latest Qiskit updates.

Stage C brings independent validation of proposed systems. It is not a demonstrated utility-scale result.

Selected research and commercial users can test error-aware programming based on D-Wave's dual-rail gate-model architecture. The beta provides simulator access while the corresponding gate-model hardware remains forthcoming.

A hybrid method uses QAOA-derived correlations to guide Gurobi while preserving a hard constraint. Computational benchmarks reached good solutions sooner on balanced graph-partitioning instances, motivating further tests across more varied constraints.

Quantinuum reports a 4.28× logical improvement over physical Clifford error, without post-selection.

The center provides Majorana 2 hardware for independent DARPA testing.

Published 22 Sep; announcement dated 17 Sep. The collaboration concerns future neutral-atom systems.

IonQ tested classical decoding against simulated workloads reaching 408 logical qubits and more than 31.5 million operations. A standard CPU kept decoding overhead low in the tested noise model; this is not a 408-logical-qubit hardware demonstration.

The authors propose evaluating logical qubits through reliability, scale, capability and runtime. Their framework requires repeated correction, fault-tolerant universal operations and timely feedback, helping distinguish small demonstrations from architectures intended for long computations.

IonQ's architecture-specific estimate models secp256k1 key recovery with 19,397 physical qubits, 1,457 logical qubits and 25.7 days per attempt. It is a future-machine resource study; no wallet or live cryptographic system was broken.

Quantinuum reports Helix memory error of 4.6×10⁻⁵ per logical qubit per round without post-selection. Separate Clifford-gate experiments also improved on physical-level performance, demonstrating complementary error-correction building blocks on Helios.

Pasqal reports four rubidium atoms held in optical traps supplied by one photonic chip, with lifetimes around 27.5 seconds. The experiment explores a compact alternative to bulky optics for future neutral-atom processors.

QuEra targets a future system with more than 1,000 logical qubits and roughly a billion reliable logical operations. The proposed machine follows Libra and is intended for initial use in 2028–2029; these specifications remain roadmap targets.

NIST advanced nine additional post-quantum signature candidates to another evaluation round. This expanded the research pipeline rather than approving nine new standards; candidate status can change as cryptanalysis continues.

Anza and Firedancer independently developed initial Falcon signature implementations for Solana's post-quantum migration research. The Foundation describes preparation for a potential network transition; ordinary Solana wallet authorization has not thereby become post-quantum secure.

Draft SP 800-230 proposes six SLH-DSA parameter sets aimed at faster verification and smaller signatures. They impose a limit of 2²⁴ signatures per key, making the proposal relevant to carefully bounded signing workloads.

Theoretical circuits could solve 256-bit elliptic-curve discrete logarithms with fewer than 500,000 physical superconducting qubits under specified error and connectivity assumptions. This is not demonstrated hardware. April 15 revision patches proof-system software.

A theoretical architecture estimates cryptographically relevant Shor algorithms with as few as 10,000 physical atomic qubits. A 26,000-qubit configuration could solve P-256 in days under assumptions; substantial engineering challenges remain.

Google reports experimentally demonstrated error-correction circuits that alternate their construction over time. These approaches reduce coupler requirements, address leakage and enable different gates, expanding the design options for future processors.

Experiments on arrays of up to 448 atoms combine repeated error correction, logical operations and qubit reuse. A four-round characterization circuit shows improved error suppression with increasing code size; the measurements address distinct tasks.